HBM4 (High Bandwidth Memory 4)

Notes

The customisable logic base die draws foundries such as TSMC into what used to be purely a DRAM maker's product.

Overview

HBM4 is the sixth generation of High Bandwidth Memory, after HBM, HBM2, HBM2E, HBM3 and HBM3E, defined by JEDEC as a stack of DRAM dies joined by through-silicon vias that sits beside a processor inside the same package and talks to it over a very wide interface. It doubles the interface to 2048 bits per stack, which is how it reaches roughly twice the bandwidth of HBM3 at similar pin speeds. Its main customers are AI accelerators and high-performance computing chips, which are limited as much by memory bandwidth as by compute.

How it works

An HBM4 stack has a base die at the bottom, with up to 16 DRAM dies above it, all connected vertically. The JEDEC standard defines 32 independent channels per stack, each split into two pseudo-channels, double the 16 channels of HBM3. At the transfer rate of up to 8 Gb/s that JEDEC announced, the 2048-bit interface gives up to about 2 TB/s per stack. The standard allows 4-high to 16-high stacks with 24 Gb or 32 Gb dies, so a 16-high stack of 32 Gb dies holds 64 GB. It also keeps compatibility with HBM3 controllers.

Memory makers have announced parts that run faster than the JEDEC baseline: SK hynix reported more than 10 Gb/s, Micron more than 11 Gb/s and Samsung up to 13 Gb/s. A bigger change is the base die. In earlier generations it was largely a standard part, but for HBM4 it can be made on a logic foundry process, and some large customers plan to put their own logic into it.

JEDEC also raised the allowed stack height from 720 to 775 micrometres, which let makers reach 16 dies while keeping microbump bonding rather than moving to hybrid bonding in this generation.

Examples

• JEDEC published JESD270-4 in April 2025, and the current revision listed on its site is JESD270-4A, published in December 2025.
• SK hynix announced in September 2025 that it had completed HBM4 development and prepared mass production, reporting more than 10 Gb/s per pin.
• Micron lists an HBM4 product with a 2048-bit interface at more than 11 Gb/s, giving more than 2.8 TB/s per stack.
• Samsung describes HBM4 built on its 1c DRAM process with a base die made on its 4 nm foundry process.

Why it matters

For AI and HPC accelerators, the number of HBM stacks and their speed largely set how fast data reaches the compute units, so HBM4 supply and qualification shape product roadmaps. Memory designers, controller and PHY engineers, package integration engineers and stacking process engineers all work with it, and the custom base die brings logic designers into memory decisions.

Related terms

• HBM3E
• TSV
• Die stacking
• JEDEC

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.