Acronym · Memory & Storage
DDR4 (Double Data Rate 4)
The JEDEC main memory generation whose standard was published in September 2012, running 1600 to 3200 MT/s at 1.2 volts with bank groups and optional bus parity.
It remains widely used in embedded, networking and older server platforms.
- Type
- Acronym
- Domain
- Memory & Storage, DRAM standards
Notes
DDR4 supply tightened sharply from 2025 as makers converted capacity to DDR5 and HBM.
Overview
DDR4, short for Double Data Rate 4 SDRAM, is the fourth generation of the JEDEC standard for main-memory DRAM chips and modules, published by JEDEC as JESD79-4 in September 2012. It runs at data rates from 1,600 to 3,200 megatransfers per second per pin, at a core and I/O voltage of 1.2 volts, and introduced bank groups to keep throughput up at those speeds. Newer generations have followed, but DDR4 parts are still offered for industrial, automotive and enterprise equipment.
How it works
Like earlier DDR generations, DDR4 transfers data on both edges of the clock and fetches several words from the array at once to feed a fast external bus from a slower internal core; it uses an 8n prefetch. The new element is bank groups. A DDR4 device has 16 internal banks arranged in up to four bank groups, so separate activate, read, write or refresh operations can be under way in different groups. Memory controllers spread accesses across groups to keep the bus busy, which JEDEC says improves efficiency and bandwidth, especially with small accesses.
The electrical interface also changed. Voltage dropped from DDR3's 1.5 volts to 1.2 volts, and a separate 2.5 volt supply (VPP) powers the word lines, replacing the internal charge pumps DDR3 used. The data bus moved from SSTL to a pseudo open drain interface (POD12), the data reference voltage became internally generated, and on-die termination gained a park mode and more resistance values. JEDEC also added improved training modes and a geardown mode for 2,667 MT/s and above.
The current JEDEC revision, JESD79-4D from July 2021, covers devices from 2 Gb to 16 Gb in x4, x8 and x16 widths. The chips are used on memory modules and also soldered directly onto boards in embedded designs.
Examples
- An embedded networking SoC with a 64-bit DDR4 interface running soldered-down x16 DDR4 chips at 2,400 or 3,200 MT/s.
- Registered DDR4 DIMMs in a previous-generation server platform, still deployed in data centres.
- Micron DDR4 components offered for the extreme temperature requirements of industrial and automotive applications.
- A memory controller spreading reads across different bank groups so that several operations overlap.
Why it matters
DDR4 controllers and PHYs are still designed into SoCs for embedded, networking, industrial and automotive markets, where long product life and established supply matter more than peak bandwidth. Memory controller and PHY designers, memory applications and validation engineers, board designers and obsolescence managers all deal with it.
In the chip lifecycle, the choice of DDR4 or a newer standard is made at architecture, controller and PHY IP is integrated and verified against JEDEC timing, interfaces are trained and characterised on first silicon with several DRAM vendors' parts, and long-term supply is managed through production and end of life.
It matters most to: DDR/LPDDR PHY Design Engineer, Memory Applications Engineer, Memory Controller Design Engineer, Memory Interface Validation Engineer, Product Lifecycle & Obsolescence Manager
Common confusions
- Not the same as LPDDR4
- LPDDR4 is a separate JEDEC low-power standard for mobile devices, with a different interface and channel structure. It is not a low-power version of DDR4 and the two are not interchangeable.
- Not the same as DDR4 megahertz ratings
- Speeds such as DDR4-3200 are data rates in megatransfers per second. The clock itself runs at half that rate, 1.6 GHz in that case, because data moves on both clock edges.
Related standards
- JEDEC JESD79-4D (DDR4 SDRAM)
Sources
- JESD79-4D: DDR4 SDRAM Standard (July 2021) (opens in a new tab), JEDEC, 2026-10-22
- JEDEC Announces Publication of DDR4 Standard (press release, 25 September 2012) (opens in a new tab), JEDEC, 2026-10-22
- DDR3 to DDR4 memory (opens in a new tab), Micron Technology, 2026-10-22
- DDR4 SDRAM (opens in a new tab), Micron Technology, 2026-10-22
Related terms
Part of the Memory & Storage glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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Standards
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary