Critical area

Notes

Critical area analysis lets designers trade a small area increase for a measurable yield gain, the core of layout DFM.

Overview

Critical area is the part of a chip layout in which a defect of a given size, landing there, would cause a fault such as a short between two wires or a break in one. It depends on the size of the defect and on how tightly the layout is drawn, and it is worked out separately for each layer and each type of fault. Combined with a fab's data on how many defects of each size occur, it lets engineers predict how much yield a particular layout will lose to random defects.

How it works

Picture a circular particle of a given diameter. For shorts, the critical area is the region where its centre must fall to bridge two neighbouring wires; for opens, it is where it would cut a wire. A particle smaller than the gap between wires cannot cause a short, while a large one can bridge wires over a wide region, so critical area grows with defect size and with layout density.

Fabs measure how defect counts fall with size, typically with electrical test structures that have lines at different spacings to catch shorts, and other structures to catch opens. The distribution follows a power law, so the yield risk is concentrated in defects close to the minimum feature size: smaller ones have little critical area and larger ones are scarce. Averaging critical area over the size distribution gives one figure per layer and fault type.

In the simple Poisson yield model, yield falls exponentially as the product of defect density and critical area grows; Murphy's and the negative binomial models allow for defect density that varies across wafers. Tools such as Siemens Calibre YieldAnalyzer run critical area analysis on all base and interconnect layers using the foundry's defect densities per layer and fault type. Critical area covers only random defects; systematic and parametric losses need other methods.

Examples

• Running critical area analysis on a large SoC before tapeout, with the foundry's defect densities for each layer, to estimate random-defect yield.
• Test structures with lines at several spacings, used to measure how often shorts occur for each defect size.
• Comparing two routing versions of a block, where the one with wider spacing has less critical area for shorts.
• A die over 600 square millimetres, where Siemens notes only about 70 to 80 gross dies fit on a wafer, so small yield losses are costly.

Why it matters

Critical area connects a fab's defect data to a specific design, so it explains why two chips of the same size on the same process can yield differently. DFM and yield-aware design engineers use it to find and fix defect-prone layout before tapeout and yield engineers use it to separate design sensitivity from fab defectivity.

Related terms

• D0
• DFM
• Functional yield
• Kill ratio

Where it appears on the Hub

Used on 4 pages of the Hub. In each group, the pages that mention it most come first.