Standard · Standards & Organisations
AMBA (Advanced Microcontroller Bus Architecture)
Arm's family of open on-chip interconnect specifications, including AHB, APB, AXI, ACE and CHI, which define how IP blocks communicate inside an SoC. Although authored by Arm, the specifications are freely available and widely used with non-Arm cores.
- Also known as
- AXI, AHB, APB, CHI
- Type
- Standard
- Domain
- Standards & Organisations, Consortia & alliances
- Also relevant to
- Design & Architecture
Notes
AXI has become the de facto interface for third-party IP delivery, so IP vendors quote AXI compliance as a default.
Overview
AMBA (Advanced Microcontroller Bus Architecture) is Arm's family of on-chip interconnect specifications that define how processors, memories, accelerators and peripherals inside a system on chip exchange data. Arm publishes the specifications openly and royalty-free, so they are used with many processor architectures, not only with Arm cores. AMBA is a set of protocols rather than one bus, ranging from a simple register bus to fully cache-coherent links.
How it works
Each AMBA protocol defines the signals, handshakes and transaction rules at the edge of an IP block, so blocks from different teams or vendors can be joined through a fabric without custom glue logic. APB is a compact, low-power bus for configuration registers and low-bandwidth peripherals. AHB is a simpler, low-latency bus used mainly around microcontroller-class cores. AXI separates the address and data phases of a transfer, supports bursts described by a single start address and allows many transactions in flight, which suits high-bandwidth traffic to memory and accelerators.
Later generations added coherency. ACE extended AXI so that caches in different processors could stay consistent, and ACE-Lite gives one-way coherency for devices without caches of their own. AMBA 5 introduced CHI, a packet-based protocol whose separate protocol and transport layers let it scale from small crossbars to large mesh networks, and Arm has since defined CHI C2C for links between chiplets. Other members of the family cover trace (ATB), streaming (AXI-Stream) and clock and power control (LPI).
The specifications are revised in lettered issues, so IP blocks and interconnects must state which issue and options they support. AMBA defines interfaces only: performance depends on the interconnect built around them.
Examples
- A microcontroller in which AHB links the core to flash and SRAM, while timers and serial ports sit on a slower APB segment.
- An AI accelerator delivered with AXI ports so that it can be integrated into SoCs built around different processor cores.
- A server processor whose cores, caches and memory controllers are joined by a CHI-based mesh interconnect.
- Network-on-chip IP that accepts AMBA CHI, ACE, AXI, AHB and APB traffic at its edges and carries it internally as packets.
Why it matters
AMBA is the common language of SoC integration. SoC architects decide which protocol each subsystem uses, interconnect and NoC designers build fabrics that speak them, IP vendors ship blocks with AMBA ports, and verification engineers use protocol checkers and verification IP to prove compliance. A mismatch in protocol issue or optional features between two blocks is a familiar integration bug.
Related terms
Part of the Standards & Organisations glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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Used on 14 pages of the Hub. In each group, the pages that mention it most come first.
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