Accellera (Accellera Systems Initiative)

Notes

Owns UVM, the Portable Test and Stimulus Standard and SystemRDL; it absorbed the Open SystemC Initiative in 2011.

Overview

Accellera Systems Initiative is an independent, not-for-profit industry organisation that develops standards for system-level design, modelling and verification of electronic systems, and then contributes mature ones to the IEEE for formal standardisation. Its members include EDA vendors, chip companies and IP suppliers, who use it to agree formats and methods that every tool can support. Several of the standards chip teams use daily, such as UVM, SystemC and IP-XACT, have passed through Accellera.

How it works

Accellera grew out of mergers of earlier industry groups: Open Verilog International and VHDL International combined to form the Accellera Organization, which later joined with The SPIRIT Consortium and the Open SystemC Initiative, taking its current name.

Work happens in technical working groups made up of member companies. A group drafts a specification, often with a reference implementation, and the board approves it for release. When a standard is stable, Accellera hands it to the IEEE, which publishes it as an IEEE standard and maintains it from then on, while Accellera continues to support user communities such as those for SystemC, UVM and IP-XACT. Universal Verification Methodology (UVM) became IEEE 1800.2, SystemC is IEEE 1666, IP-XACT is IEEE 1685, and power intent written in the Unified Power Format is defined by IEEE 1801.

Accellera also keeps standards of its own, such as the Portable Test and Stimulus Standard (PSS), SystemRDL for register descriptions, and newer standards on clock domain crossing and a functional safety language. Some of the resulting IEEE standards, IEEE 1801-2024 among them, are offered at no cost through the IEEE GET Program.

Examples

• A verification team building a reusable testbench on the UVM base class library defined in IEEE 1800.2.
• A virtual platform written in SystemC so that software can run before silicon exists.
• An IP vendor delivering an IP-XACT description so that a customer's tools can integrate the block automatically.
• A register map written once in SystemRDL and used to generate RTL, documentation and verification models.
• A design team checking clock domain crossings in a way aligned with Accellera's Clock Domain Crossing standard, so results compare across tools.

Why it matters

Accellera standards let verification environments, IP packages and power intent move between tools from different vendors, which reduces lock-in and the cost of reuse. Verification methodology engineers, UPF power intent engineers, IP integration teams and standards representatives follow its working groups because what is agreed there later shapes the tools they use.

Related terms

• IEEE 1801
• IEEE 1666
• IEEE 1685
• Si2
• UVM
• PSS

Where it appears on the Hub

Used on 15 pages of the Hub. In each group, the pages that mention it most come first.