Technology · Packaging & Assembly
Advanced packaging
Packaging technologies that go beyond a single die on a lead frame or laminate, such as fan-out, 2.5D interposers, 3D stacking, hybrid bonding and chiplet integration.
They raise bandwidth and density between dies and are central to AI and high-performance chips.
- Type
- Technology
- Domain
- Packaging & Assembly, Advanced packaging
Overview
Advanced packaging is the family of chip packaging technologies that go beyond a single die wire-bonded or flip-chip mounted on a lead frame or laminate substrate, connecting dies far more densely than a circuit board can. It includes fan-out wafer-level packaging, 2.5D integration on silicon interposers or bridges, 3D stacking of dies, and hybrid bonding. These methods are central to AI processors, high bandwidth memory and chiplet-based designs.
How it works
The common aim is to bring dies closer together with many more, shorter connections. In fan-out wafer-level packaging, dies are embedded in a moulded wafer and fine wiring layers are built over them, giving more connections than the die alone could fit, without a laminate substrate. In 2.5D integration, several dies sit side by side on a silicon interposer, or are linked by small silicon bridges embedded in the substrate, with wiring far finer than any board. In 3D integration, dies are stacked and connected vertically by through-silicon vias and micro-bumps, as in high bandwidth memory.
Hybrid bonding goes further, joining copper pads on two dies or wafers directly, without solder, at pitches of a few micrometres. That gives very high connection density and is used for stacked image sensors, stacked cache and other 3D designs.
These steps borrow from wafer fabs: lithography, plating, chemical mechanical polishing and wafer bonding. Foundries now offer packaging platforms of their own, such as TSMC's CoWoS and SoIC and Intel's EMIB and Foveros, alongside the largest assembly and test companies. Standards such as UCIe define how dies from different suppliers connect inside one package, and known good die testing becomes essential, since one bad die can scrap a whole assembly.
Examples
- An AI accelerator with its processor die and several HBM stacks on a silicon interposer.
- A smartphone processor in a fan-out package that places memory above it.
- A processor with extra cache memory stacked on top by hybrid bonding.
- A chiplet-based server processor whose dies are linked by silicon bridges in the substrate.
- A stacked image sensor in which the pixel layer is bonded to a logic layer beneath it.
Why it matters
Advanced packaging now limits how many leading AI accelerators can be built, so it receives heavy investment from foundries, OSATs and governments. Package architects, process engineers, design kit and EDA teams, thermal and reliability engineers and test engineers all work on it, and chip architects must plan for it from the start.
In the chip lifecycle, the packaging approach is chosen at architecture alongside the die partitioning, co-designed with the dies during implementation, qualified with the product, and ramped with its own capacity planning.
It matters most to: 3D Stacking & Hybrid Bonding Engineer, Fan-Out Wafer-Level Packaging Engineer, Foundry Advanced Packaging Enablement Engineer, Head of Advanced Packaging Technology, Package Architect
Common confusions
- Not the same as system in package
- A system in package combines several chips and components in one package, often with conventional assembly. Advanced packaging refers to the dense interconnect methods that some systems in package use.
- Not the same as chiplet
- A chiplet is a die designed to work with others in one package. Advanced packaging is the technology that connects them.
- Not the same as heterogeneous integration
- Heterogeneous integration means combining different dies, processes or materials in one package. It describes the goal; advanced packaging methods are how it is done.
Related standards
- UCIe (Universal Chiplet Interconnect Express) specification, UCIe Consortium
Sources
- Specifications (opens in a new tab), UCIe Consortium, 2026-10-22
- What are Chiplets? (opens in a new tab), Synopsys, 2026-10-22
- Packaging (Knowledge Center) (opens in a new tab), Semiconductor Engineering, 2026-10-22
- Advanced packaging (semiconductors) (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
- Three-dimensional integrated circuit (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Packaging & Assembly glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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