Chip Economics / Accelerator directory Accelerator Directory
Chips built to run AI workloads (devices, not startup programmes), with process node, packaging architecture, HBM configuration and an estimated four-layer manufacturing cost bridge, each layer tied to its cost method note once curated. Related: chip cost calculator · cost bridge chart · price/performance frontier
What this register covers, and what it does not
Devices register build state: Demonstration. 8 of 8 records are still samples that no editor has checked against public sources; every figure on them is labelled. How build states work
Known gaps (6)
- No device classified in the register as: GPU accelerators
- No device classified in the register as: Custom AI processors (ASIC)
- No device classified in the register as: Wafer-scale processors
- No device classified in the register as: Server processors (CPU)
- No device classified in the register as: FPGAs and adaptive parts
- 8 of 8 devices not yet assigned a device class
Trainium2
TSMC N596GB HBM3Sample data
~US$2,460 est. costSample estimate, work in progress
MI300X
TSMC N5/N6192GB HBM3Sample data
~US$4,970 est. costSample estimate, work in progress
WSE-3 (wafer-scale)
TSMC 5nmSample data
~US$48,000 est. costSample estimate, work in progress
TPU v5p
TSMC N595GB HBM2ESample data
~US$2,160 est. costSample estimate, work in progress
Gaudi 3
TSMC N5128GB HBM2ESample data
~US$2,650 est. costSample estimate, work in progress
B200
TSMC 4NP192GB HBM3ESample data
~US$6,660 est. costSample estimate, work in progress
GB200 (per GPU)
TSMC 4NP192GB HBM3ESample data
~US$6,870 est. costSample estimate, work in progress
H100
TSMC 4N80GB HBM3Sample data
~US$3,320 est. costSample estimate, work in progress