Cerebras
WSE-3 (wafer-scale)
Illustrative sample data. No editor has checked this record against public sources yet. Figures marked Sample are placeholders, not verified data.
- Process node
- TSMC 5nmSample
- Die size
- 46,225 mm²Sample
- Packaging
- OTHERSample
- TDP
- 23000WSample
- Throughput
- 125,000 TFLOPsSample
- Release year
- 2024Sample
Estimated manufacturing cost
US$48,000Sample estimate, work in progress
Logic die: $35000.00 (73%)Packaging: $9000.00 (19%)Test: $4000.00 (8%)
- Logic die: sample figure, no method note linked yet
- Packaging: sample figure, no method note linked yet
- Test: sample figure, no method note linked yet
Work in progressThe total is the sum of the layers shown; it stays a sample estimate until every layer names its cost method note. Suggest a source or a correction
Model your own assumptions in the chip cost calculator, or compare against other accelerators on the cost bridge chart and price/performance frontier.