Tools: planning
A Hub lifecycle laid out as a plan: phases, gates and discipline tasks with their relative effort, the guides, checklists and decisions behind them, and the order of work. Read only, built from the public lifecycle data, with no dates or durations.
| Row | WBS | Item | Kind | Relative effort | Predecessors | Step | Role | On the Hub |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | Concept & Feasibility | Phase |
| ||||
| 2 | 1.1 | Concept approval | Gate | 1 | ||||
| 3 | 1.2 | SoC architecture and specificationHands on: Architecture specification; Performance model | Task | Medium | 2 | 2 | SoC Architect | |
| 4 | 1.3 | System modelling and virtual prototypingHands on: Architecture model | Task | Small | 2 | 2 | Virtual Prototyping Architect | |
| 5 | 1.4 | Performance and power analysisHands on: Performance and power targets | Task | Small | 2 | 2 | Power Architect | |
| 6 | 1.5 | IP integrationHands on: IP selection list | Task | Small | 2 | 2 | RTL Integration and Chip Assembly Engineer | |
| 7 | 1.6 | SoC RTL design | Task | Small | 2 | 2 | Digital Design Engineer | |
| 8 | 1.7 | Full-chip verification | Task | Small | 2 | 2 | Verification Engineer | |
| 9 | 1.8 | Foundry and processHands on: Technology readiness assessment; Process design kit | Task | Medium | 2 | 2 | Process / Device Engineer | |
| 10 | 1.9 | Packaging and testHands on: Package design | Task | Small | 2 | 2 | Test Engineer | |
| 11 | 1.10 | Product managementHands on: Business case | Task | Small | 2 | 2 | Product / Program Manager | |
| 12 | 1.11 | TR1: Technology feasibility | Gate | 3; 4; 5; 6; 7; 8; 9; 10; 11 | 3 |
214 more rows for registered members.
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