Studying latch-up, a fault where a CMOS chip draws large current through unwanted parasitic structures and can burn out, and designing to avoid it.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Device physics courses, ESD and layout rule training, and work with protection and test results.
Register version 1.