1. Purpose and scope
Implementation on a structured ASIC is physical design with most of the chip already fixed. The transistors, the lower routing, the clock and power networks and the positions of the memories and input and output cells cannot move. What the team controls is which configurable cells become which logic, where registers are formed, and how the custom layers will route the connections. This stage produces the netlist that settles the first two; Customer Design Closure & Sign-off settles the third.
The netlist is built in steps that each feed the next. The converted design, or the customer's RTL, is synthesised to the configurable cell library and the fixed memories with the customer's constraints. Test logic is inserted using the platform test architecture: the design's registers are connected into the base scan structure, and memory self-test and boundary scan are added as the test plan sets out. A trial placement on the fixed array then checks that the netlist with test fits and that timing can close, before anyone freezes it. Formal equivalence checks keep the netlist tied to the agreed design through each step.
The stage opens when the converted design baseline is agreed, or, for a design that arrives as RTL, when the customer design is accepted. It closes at customer netlist freeze, which sits on the Feature complete step of the maturity scale: all planned functions are in the netlist, and from here only reviewed changes are accepted, each with its effect on timing and schedule stated. The netlist is reviewed with the customer before the freeze, so late functional changes do not reach placement and routing.
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