A process design kit, from planning its scope and supported tool flows through device models, design rules, physical verification and extraction decks, technology files, PCells and symbols, standard cell and foundation IP libraries, DFM rules and fill, and kit quality assurance, to alpha, beta, pre-production and production releases of rising maturity, customer support and updates, and the kit's end of life. The output is the kit that every chip on the node is designed and signed off with.
Process design kit (PDK) development lifecycle: 13 stages and 16 gates, from PDK Planning & Scope to PDK End of Life.
13 stages and 16 gates, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
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A dashed sign with a TR tag is a technical readiness review gate.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding what the design kit must contain and support: the devices and options it offers, the design styles it serves, the tool categories and flows it must run in, the foundation IP that comes with it, and the release plan with the maturity each release must reach.
PDK scope approval gatePDK plan and tool support baselined gate
Turning the process's capabilities and limits into written layout rules: widths, spaces, enclosures, densities and the special rules for each layer and device, collected in the design rule manual.
Building the SPICE compact models designers simulate with: fitted to measurements from baseline silicon, with process corners, statistical and mismatch models, and the reliability and ageing models that predict how devices change over their life.
Device models fitted to silicon gateTR1, technical readiness review
Coding the design rules as rule decks the physical verification tool categories run: design rule checks, layout versus schematic, antenna, density and electrical rule checks, each checked against layouts written to pass and to fail every rule.
Describing the interconnect stack so tools can calculate resistance and capacitance: the interconnect technology file, the extraction decks for each supported tool category, and the electromigration and current density rules, correlated with measurements on silicon test structures.
Building what designers place and draw with: the layout technology file and layer map, parameterised cells that generate correct device layouts, schematic symbols and device parameters.
Designing and characterising the foundation IP that most designs on the node need: standard cell libraries in their chosen cell architectures and threshold voltage options, IO libraries and memory compilers, with their timing, power and noise views, abstracts and library QA, released in step with the kit's maturity.
Adding the design for manufacturability content that protects yield beyond the minimum rules: recommended rules, lithography hotspot checks, critical area guidance and the fill decks that keep layer density within the process window.
Checking the kit as a whole before a wide release: a library of QA test cases and QA designs run through every supported tool category, regression on every change, consistency checks between models, rules, decks, PCells and libraries, and certification of the reference flows.
Releasing the pre-production kit, with models correlated across corners and rules near final, so customers can design products for tape-out at an agreed risk, and supporting those design starts while the process completes its qualification.
Pre-production PDK release gateProduction readiness review gateTR3, technical readiness review
Releasing the production kit once the process is qualified: final models correlated to risk production silicon, validated sign-off decks and silicon-validated foundation IP, after which the kit is under formal change control.
Supporting the designers who use the kit: answering questions, logging and fixing errata, issuing update releases with clear notes on what changed and who is affected, and following process changes into the kit.
Retiring a kit version or the kit for a node: telling users which versions stop being supported and when, guiding them to a newer version or another node, and archiving the kit so existing designs can still be reproduced.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.