A new package technology developed by an assembly and test provider or a foundry packaging group, from the technology roadmap and customer drivers through the package concept and test vehicles, materials and substrate, process modules such as bumping, redistribution layers, interposers and hybrid bonding, equipment, process integration, reliability and board-level qualification, the package design kit and assembly design rules, the pilot line and yield learning, joint development and qualification with lead customers, and the capacity ramp to the technology's end of life. Using an existing package in a multi-die product is covered by the chiplet lifecycle.
Package technology development lifecycle: 12 stages and 19 gates, from Technology Roadmap & Customer Drivers to Technology End of Life.
12 stages and 19 gates, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
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A dashed sign with a TR tag is a technical readiness review gate.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding which new package technology to develop and why: reading customer and market drivers such as bandwidth between dies, power delivery, thermal limits, form factor and cost, placing the technology on the packaging roadmap, finding lead customers and agreeing a joint development with them.
Technology roadmap approval gateJoint development agreement signed gate
Turning the drivers into a package concept: the structure, interconnect density, die arrangement, materials direction and target ground rules, checked by early electrical, thermal and mechanical modelling, then designing the test vehicles, daisy chains and monitor structures that will prove the technology on real hardware.
Selecting and developing the materials the new package depends on: substrate or interposer technology and its stack-up, dielectrics, underfills, mould compounds, thermal interface materials, solders and bonding layers, with suppliers, measured properties and an early view of supply and cost.
Developing each new unit process to capability: wafer bumping and copper pillars, redistribution layers, fan-out moulding, through-silicon vias, interposer fabrication, temporary bonding and thinning, die-to-wafer and wafer-to-wafer hybrid bonding, fine-pitch flip chip attach, underfill and moulding, each with its own targets, process windows and measurements.
Choosing, installing and qualifying the tools the new processes need, such as bonders, plating and deposition tools, lithography for redistribution layers, grinders, dicing, inspection and metrology, from evaluation and demonstration runs to acceptance, process matching and release for the pilot line.
Joining the modules into one full assembly flow and building complete test vehicles on it, measuring electrical continuity, warpage, alignment, voids and early failures, correlating the models with hardware, and freezing a process baseline that reliability testing, the design kit and lead customers can rely on.
Proving the technology lasts: component-level stress tests to JEDEC methods such as preconditioning, temperature cycling, humidity and high temperature storage, board-level reliability under thermal cycling, drop and bending where the market needs it, electromigration of bumps and redistribution lines, and failure analysis of every failure, ending in a technology qualification report.
Packaging what customers need to design on the new technology: assembly design rules, substrate and interposer design rules, stack-up and material data, electrical, thermal and mechanical models, bump and pad libraries, rule checking decks and reference designs, released as a versioned package design kit with its limits stated.
Running the qualified flow on a pilot line with production-intent tools, materials and work instructions, building lots repeatedly to learn yield, find and remove defect sources, set inline controls and known good die rules, and show that yield and cycle time are on a credible path to volume.
Pilot line ready gateYield readiness gateTR3, technical readiness review
Building and qualifying lead customers' real products on the new technology under the joint development agreement: co-design reviews against the design kit, sample builds on the pilot line, the customer's product-level qualification and system evaluation, failure analysis and corrective actions, and the customer's approval for volume.
Releasing the technology to volume manufacturing and adding capacity to meet demand: copying the qualified flow to more tools and sites, securing substrate and material supply, keeping yield, quality and delivery on target while volume grows, reducing cost, and reviewing when the technology should be extended or refreshed.
Volume production release gateRamp complete gateTechnology refresh review gate
Withdrawing the package technology when demand, cost or a successor make it no longer worth running: the discontinuance notice to customers, last-time-buy plans, final builds, the run-out of materials and substrates, tool redeployment and the archive of process, quality and reliability records.
Technology discontinuance notice gateLast assembly build gate
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.