Mapping the design onto FPGAs to run real software and interfaces at speeds closer to the final chip before silicon exists. Covered in full on its own function page.
This sub-function's own lane. See it beside the other sub-functions of functional verification on the function's swimlane.
Chevrons show maturity by the end of each stage and open that stage's row below; diamonds are freeze and sign-off points; triangles are the lifecycle's gates.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.