1. Purpose and scope
This stage produces the bitstream: the configuration file that turns the commercial device into the product's logic. There is no mask set, foundry or chip package to wait for, so the cost of a mistake is lower than for a chip, but the stage still decides whether the design runs reliably across voltage, temperature and every unit built. A design that only just meets timing, or meets it because some paths were never constrained, can pass in the lab and fail in the field.
The vendor's tools perform synthesis, placement and routing onto the fixed fabric, so the team's levers are the design source, the constraints, the tool settings and floorplanning. Timing closure is often the longest part of the stage on a full or fast design, and it is common to feed changes back into the logic to shorten paths.
In scope: final synthesis and implementation from the signed-off source, timing analysis across the device's timing corners, resolution of violations, utilisation review, bitstream encryption and authentication settings, bitstream generation and archiving, and bring-up planning. Out of scope: logic feature changes, which need a reviewed bug report and reverification, and hardware testing on the board.
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