Starts base array design once the architecture is frozen: the array tile and cells are laid out, the fixed blocks are integrated with the clock and power networks and the verification environment is built alongside. The physical design, library and verification leads run it together.
MustThe base array architecture is frozen and the layer split is locked with the foundry.
SeeDecision: Which layers of the metal stack to leave customisable
MustThe process design kit, fixed block IP and tool versions for the base are locked.
SeeFlow: Moving PDK or tool versions mid-projectFlow: Taking a new IP version into a frozen design
MustA base verification plan outline lists the fixed blocks, networks, cells and test structures to verify.
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