Use to decide that test structures, constraints, the reference synthesis and models are ready for an integrator. Run by the IP program manager with the DFT implementation engineer and the soft IP hardening engineer presenting.
MustThe decision owner for this gate is named and has confirmed attendance.
MustThe required reviewers are invited, including at least one representative of the SoC programs that will integrate the block.
MustThe evidence pack was circulated early enough for reviewers to read it before the review.
MustFormats and operating conditions are confirmed with the SoC teams before the review, not discovered in it.
ShouldThe SoC DFT architect and a SoC timing lead attend.
MustIP verification sign-off has passed.
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