Chip lifecycle / Checklists / FPGA chip lifecycle / Place-and-Route & Timing Software: entry checklist

Place-and-Route & Timing Software: entry checklist

Use when the fabric and bitstream format are frozen and the software team starts adding the device to every engine of the design software. Run by the place-and-route software lead.

1. Inputs

MustThe bitstream format is frozen and held under change control.
Evidence
Bitstream format specification
Owner
Configuration architect
SeeDecision: Bitstream format and configuration interfaces
MustThe fabric architecture specification and the hard IP device model entries are available.
Evidence
Fabric architecture specification
Owner
FPGA fabric architect
MustTile timing views are available at a stated version, with a date for the final views.
Evidence
Tile timing views
Owner
Circuit design engineer

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