Guides code review of every FPGA block before design code complete. The FPGA design lead runs it with a peer designer and a verification engineer.
MustThe material under review is a tagged version, named in the record.
MustReviewers received the material and this checklist early enough to prepare.
ShouldAt least one reviewer did not take part in the work under review.
ShouldThe scope of the review and anything excluded are stated at the start.
MustCode follows the coding guidelines.
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