Tape-out

Disciplines

• Workload and model analysis^OO
  • Physical Design & Package Sign-off: maturity 1.0, Complete. Reference workloads and accuracy baselines released for runs on emulation, then on silicon, in benchmarking and in customer qualification; the set is reviewed as models change.
  • Tape-out: maturity 1.0, Complete. Reference workloads and accuracy baselines released for runs on emulation, then on silicon, in benchmarking and in customer qualification; the set is reviewed as models change.
  • System Hardware: Boards, Power & Cooling: maturity 1.0, Complete. Reference workloads and accuracy baselines released for runs on emulation, then on silicon, in benchmarking and in customer qualification; the set is reviewed as models change.
• Performance modelling^A
  • Physical Design & Package Sign-off: maturity 1.0, Complete. Model correlated with the verified design and released as the performance reference; used for cluster projections and compared with silicon.
  • Tape-out: maturity 1.0, Complete. Model correlated with the verified design and released as the performance reference; used for cluster projections and compared with silicon.
  • System Hardware: Boards, Power & Cooling: maturity 1.0, Complete. Model correlated with the verified design and released as the performance reference; used for cluster projections and compared with silicon.
• Accelerator architecture^A
  • Physical Design & Package Sign-off: maturity 1.0, Complete. Architecture checked against the verified design and its performance correlation; changes only through change control.
  • Tape-out: maturity Freeze, Frozen. Architecture locked in the taped-out design; changes wait for a new stepping or generation.; Architecture locked at tape-out
• RTL design^D
  • Physical Design & Package Sign-off: maturity Freeze, Frozen. Design locked from physical design on: only approved engineering change orders go in before tape-out, and silicon bugs are root caused and fixed in a new stepping.
  • Tape-out: maturity Freeze, Frozen. Design locked from physical design on: only approved engineering change orders go in before tape-out, and silicon bugs are root caused and fixed in a new stepping.
  • System Hardware: Boards, Power & Cooling: maturity Freeze, Frozen. Design locked from physical design on: only approved engineering change orders go in before tape-out, and silicon bugs are root caused and fixed in a new stepping.
• Design verification and emulation^A
  • Physical Design & Package Sign-off: maturity Freeze, Frozen. Results locked on the frozen design from physical design on: gate-level and change verification run to tape-out, then emulation runs the bring-up tests before silicon and reproduces silicon failures after it.
  • Tape-out: maturity Freeze, Frozen. Results locked on the frozen design from physical design on: gate-level and change verification run to tape-out, then emulation runs the bring-up tests before silicon and reproduces silicon failures after it.
  • System Hardware: Boards, Power & Cooling: maturity Freeze, Frozen. Results locked on the frozen design from physical design on: gate-level and change verification run to tape-out, then emulation runs the bring-up tests before silicon and reproduces silicon failures after it.
• Compiler and graph tools^A
  • Physical Design & Package Sign-off: maturity 1.0, Complete. Released for first silicon: every target workload compiles and runs end to end on emulation with checked results; later releases add performance on silicon, the production release and maintenance releases.
  • Tape-out: maturity 1.0, Complete. Released for first silicon: every target workload compiles and runs end to end on emulation with checked results; later releases add performance on silicon, the production release and maintenance releases.
  • System Hardware: Boards, Power & Cooling: maturity 1.0, Complete. Released for first silicon: every target workload compiles and runs end to end on emulation with checked results; later releases add performance on silicon, the production release and maintenance releases.
• Runtime, drivers and firmware^O
  • Physical Design & Package Sign-off: maturity 0.5, Draft. Firmware, driver and runtime run the target workloads on emulation, with gaps tracked, at pre-silicon readiness.
  • Tape-out: maturity 0.8, Feature complete. Bring-up firmware, driver and runtime feature complete and checked on emulation of the taped-out design; versions tagged for first silicon.
  • System Hardware: Boards, Power & Cooling: maturity 0.8, Feature complete. Bring-up firmware, driver and runtime feature complete and checked on emulation of the taped-out design; versions tagged for first silicon.
• Kernels, libraries and framework integration^D
  • Physical Design & Package Sign-off: maturity 0.5, Draft. Kernel library and framework integration run the target workloads on emulation at pre-silicon readiness, with gaps tracked.
  • Tape-out: maturity 0.5, Draft. Kernel library and framework integration run the target workloads on emulation at pre-silicon readiness, with gaps tracked.
  • System Hardware: Boards, Power & Cooling: maturity 0.5, Draft. Kernel library and framework integration run the target workloads on emulation at pre-silicon readiness, with gaps tracked.
• Physical design and package^A
  • Physical Design & Package Sign-off: maturity 1.0, Complete. Timing, power integrity, physical checks and package signed off at physical sign-off, with the package models released to the board teams.
  • Tape-out: maturity Freeze, Frozen. Tape-out database and package design released and locked at tape-out; package models and timing data support the boards and bring-up.^A; Tape-out database released
  • System Hardware: Boards, Power & Cooling: maturity Freeze, Frozen. Tape-out database and package design released and locked at tape-out; package models and timing data support the boards and bring-up.
• Boards, power delivery and cooling^O
  • Physical Design & Package Sign-off: maturity 0.8, Feature complete. Board, power delivery and cooling designs feature complete with the package thermal and electrical models from physical sign-off.
  • Tape-out: maturity 0.8, Feature complete. Board, power delivery and cooling designs feature complete with the package thermal and electrical models from physical sign-off.
  • System Hardware: Boards, Power & Cooling: maturity 1.0, Complete. Board, power delivery and cooling released for build; bring-up boards ready for first silicon, revised from bring-up and released for production.
• Scale-out networking^O
  • Physical Design & Package Sign-off: maturity 0.5, Draft. Collective communication plan drafted with the software teams; chip-to-chip links checked on emulation.
  • Tape-out: maturity 0.8, Feature complete. Link budget closed with the package design at tape-out; rack power and cooling checked with the board design.
  • System Hardware: Boards, Power & Cooling: maturity 0.8, Feature complete. Link budget closed with the package design at tape-out; rack power and cooling checked with the board design.
• Bring-up and silicon validation^A
  • Physical Design & Package Sign-off: maturity 0.0, Planned. Silicon validation approach planned with verification: what first silicon must show and how it is checked.
  • Tape-out: maturity 0.3, Early draft. Bring-up test content written from the verification tests and run on emulation of the taped-out design.
  • System Hardware: Boards, Power & Cooling: maturity 0.5, Draft. Bring-up plan final with the board design; debug tools and the lab set-up prepared.
• Benchmarking and performance engineering^O
  • Physical Design & Package Sign-off: maturity 0.3, Early draft. Benchmark plan final from the pre-silicon run results; the harness started on emulation.
  • Tape-out: maturity 0.3, Early draft. Benchmark plan final from the pre-silicon run results; the harness started on emulation.
  • System Hardware: Boards, Power & Cooling: maturity 0.5, Draft. Benchmark harness, automation and reporting dry run on emulation and against the performance model, including multi-chip runs.
• Test, quality and manufacturing^A
  • Physical Design & Package Sign-off: maturity 0.3, Early draft. Scan and memory test patterns generated on the signed-off design at physical sign-off, and the test plan final at tape-out.
  • Tape-out: maturity 0.3, Early draft. Scan and memory test patterns generated on the signed-off design at physical sign-off, and the test plan final at tape-out.
  • System Hardware: Boards, Power & Cooling: maturity 0.3, Early draft. Scan and memory test patterns generated on the signed-off design at physical sign-off, and the test plan final at tape-out.
• Customer enablement^A
  • Physical Design & Package Sign-off: maturity 0.5, Draft. Lead customers' models compiled and run on emulation with the pre-silicon software stack, and porting gaps fed back.
  • Tape-out: maturity 0.5, Draft. Lead customers' models compiled and run on emulation with the pre-silicon software stack, and porting gaps fed back.
  • System Hardware: Boards, Power & Cooling: maturity 0.5, Draft. Lead customers' models compiled and run on emulation with the pre-silicon software stack, and porting gaps fed back.
• Product and programme management^D
  • Physical Design & Package Sign-off: maturity 0.5, Draft. System offerings, pricing approach and supply plans prepared while the chip is made.
  • Tape-out: maturity 0.5, Draft. System offerings, pricing approach and supply plans prepared while the chip is made.
  • System Hardware: Boards, Power & Cooling: maturity 0.5, Draft. System offerings, pricing approach and supply plans prepared while the chip is made.