Test power

Notes

Managed with low-toggle fill, chain segmentation, clock staggering and shift frequency limits; a common cause of yield loss blamed on the design.

Overview

Test power is the power a chip draws while it is being tested, which for scan-based tests can be several times higher than in normal operation because test patterns switch far more of the logic at once. Too much of it causes supply droop and heat, which can make good chips fail, let marginal ones pass, or in extreme cases damage parts on the tester. Low-power design techniques cut functional power, but they do not by themselves cut test power, so it has to be managed in DFT and pattern generation as well.

How it works

Scan testing alternates two phases, and each stresses the chip differently. During shift, test data is clocked through the scan chains for many cycles. Shifting random-looking values makes roughly half the scan cells change state on each cycle, far more than in most functional operation, and the effect builds up as heat. The switching can also cause voltage drop and clock skew that make the shift itself fail.

During capture, the circuit runs for one or two fast cycles to record its response. In at-speed tests that launch and capture on consecutive clocks, heavy switching in the launch cycle can cause enough IR drop to slow critical paths, so a defect-free chip captures a wrong value. This false failure is test-induced yield loss. Voltage drop on the clock path can also stretch the clock, which can let a marginal part pass.

Tools estimate the power of each pattern, often with a weighted switching activity metric, and drop or repair patterns above a limit. Reduction techniques include holding most scan chains steady during shift, gating clocks not needed for the targeted faults, filling unspecified pattern bits so fewer cells toggle, testing blocks in turn, and slowing the shift clock. Each costs something, usually more patterns or longer test time.

Examples

• A device that failed scan tests at about 20 per cent lower frequency than expected because of IR drop caused by test power, reported in EE Journal.
• Low-power shift in a compression architecture, holding most chains steady so far fewer cells toggle on each shift cycle.
• Capture-safety checking that discards or repairs test vectors whose launch-cycle switching would be too high.
• Testing the blocks of a large SoC in sequence rather than all at once to lower average power on the tester.

Why it matters

Test power decides whether a test programme measures the chip or the test conditions. Too little control causes overkill (good parts rejected) and underkill (bad parts shipped), both of which cost money. DFT architects set the test power budget, test compression and ATPG engineers keep patterns within it, and test engineers and power integrity engineers check it on silicon.

Related terms

• Scan chain
• At-speed test
• Test escape
• Guard band

Where it appears on the Hub

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