Acronym · Packaging & Assembly
SoIC (System on Integrated Chips)
TSMC's bumpless 3D stacking platform, which joins known good dice face to face or face to back using hybrid bonding at sub-10 micrometre pitch, either chip on wafer or wafer on wafer.
- Also known as
- TSMC SoIC, SoIC-X
- Type
- Acronym
- Domain
- Packaging & Assembly, Advanced packaging
Notes
Used for AMD's 3D V-Cache and increasingly combined with CoWoS in the same product as a 3D stack on a 2.5D carrier.
Related terms
Part of the Packaging & Assembly glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 2 pages of the Hub. In each group, the pages that mention it most come first.
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