Term · Test & DFT
Full scan
A DFT style in which every, or nearly every, flip-flop in the design is made scannable. It gives ATPG a purely combinational problem and very high coverage, at the cost of area and routing; partial scan converts only a subset and is now rare in digital logic.
- Type
- Term
- Domain
- Test & DFT, DFT architecture
Notes
Standard practice for digital SoCs since the 1990s; exceptions are usually clock generation, analog interfaces and a few timing-critical paths.
Related terms
- Scan chain
- Partial scan
- ATPG
- Fault coverage
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