Process · Design & Architecture
Pre-silicon release
The release of a hard IP block's signed-off layout and characterised views before test chip results are available, so that integrators can design it in early, accepting that it is not yet proven in silicon.
- Also known as
- Pre-silicon IP release
- Type
- Process
- Domain
- Design & Architecture, IP and reuse
Overview
A pre-silicon release is a release of a hard IP block whose design is finished and signed off but has not yet been measured on manufactured silicon. Its views are complete enough for a chip team to place it, close timing and verify it in their design. What it lacks is the evidence that the silicon behaves as the models say.
How it works
The IP team completes the block's layout, runs its sign-off checks and characterises it from simulation across process, voltage and temperature. It then packages the views an integrator needs: layout, abstract, timing and power models, behavioural models, integration guide and the list of known limits, and labels the release as pre-silicon.
At the same time, the block goes onto a test chip. When the test chip returns, the block is measured and compared with its models. If the results match, a silicon-proven release follows with a characterisation report. If they do not, the views or the design are updated and integrators are told what changed.
Integrators who take a pre-silicon release plan for that risk, for example by keeping a margin or by timing their own tape-out after the test chip results.
Examples
- A new interface block released to a lead customer while its test chip is still being made.
- A pre-silicon release of a clock generator whose models are updated after silicon measurement.
- An SoC team scheduling its tape-out after the test chip results of a pre-silicon block it depends on.
- A release note listing which measurements are still awaited.
Why it matters
Waiting for test chip results can add months before a block can be used. A pre-silicon release lets a lead customer start integration earlier, which matters when a new process or interface is on the critical path. The cost is risk: a silicon problem in the block becomes a problem in the customer's chip. IP product managers, IP release engineers and the integrating SoC team agree the terms.
In the Hard IP lifecycle, the pre-silicon release comes after sign-off and before test chip results; the silicon-proven release follows characterisation.
It matters most to: IP Integration & Hardening Engineer, IP Product Manager, IP Signoff and Release Engineer, IP Silicon Validation Engineer
Common confusions
- Not the same as an early access release
- An early access release may be incomplete, with parts still missing. A pre-silicon release is complete and signed off; what it lacks is silicon evidence.
- Not the same as silicon proven
- Silicon proven means the block has been measured on manufactured silicon and the results reported. A pre-silicon release has not been measured yet.
Sources
- Experts At The Table: Who Takes Responsibility? (opens in a new tab), Semiconductor Engineering, 2026-11-10
- Semiconductor intellectual property core (opens in a new tab), Wikipedia, 2026-11-10
- Agile Analog's Approach to Analog IP Design and Quality: Why "Silicon Proven" is NOT What You Think (opens in a new tab), Design And Reuse (article by Agile Analog), 2026-11-10
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 2 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary