PD engineer (Physical Design engineer)

Notes

PD headcount peaks in the months before tapeout, which is why many companies use external design services to flex it.

Overview

A PD engineer, short for physical design engineer, is the chip designer who turns a synthesised gate-level netlist into a placed and routed layout that a foundry can manufacture. The role sits between logic design and tapeout: it takes the netlist, timing constraints and the foundry's design rules, and returns a layout that meets the block's targets for power, performance and area. PD engineers usually own one block or a group of blocks, while a top-level team assembles the full chip.

How it works

Work on a block typically starts with floorplanning: deciding the block's size and shape, where large macros such as memories sit, and where the pins go. Power planning follows, laying down the grid of power and ground connections that must deliver current without excessive voltage drop. Placement tools then position the standard cells, clock tree synthesis builds the network that carries the clock to every flip-flop, and routing connects everything across the metal layers while avoiding congestion and shorts.

After each step the engineer checks timing. Static timing analysis tests every path for setup and hold violations, and the PD engineer repairs failures by resizing cells, inserting buffers, moving logic or, when the problem is structural, asking the RTL team for a change. Power integrity tools check IR drop and electromigration on the power grid, and physical verification runs design rule checks (DRC) and layout versus schematic (LVS) comparisons against the foundry's rules.

Much of the job is iteration: buffers added for timing cost power and area, and denser placement can make routing impossible. A PD engineer runs many trials, scripts the flow (commonly in Tcl) and decides which trade-offs are acceptable when targets conflict.

Examples

• A PD engineer closing timing on a CPU core block by resizing cells and adding buffers on the slowest paths reported by static timing analysis.
• Reworking a block's floorplan when routing congestion around a large memory makes the first layout unroutable.
• Running DRC and LVS until a block is clean against the foundry's rule deck before handing it to the top-level team.
• Using the open-source OpenROAD flow to take a small design through placement and routing to a GDSII layout.

Why it matters

PD engineers decide whether a design can actually be built at the planned size, speed and power, so their progress usually sets the tapeout date. They work with RTL and synthesis engineers upstream, with DFT, power integrity and physical verification specialists alongside, and with CAD teams who maintain the tools and flows.

Related terms

• Design engineer
• Tapeout
• DFM
• Yield engineer

Where it appears on the Hub

Used on 30 pages of the Hub. In each group, the pages that mention it most come first.