Artefact · Packaging & Assembly
Package design kit
The versioned set of rules, data, models and checking files that lets customers design products on one package technology, released by the assembly provider or foundry packaging group that developed it.
- Also known as
- Assembly design kit
- Type
- Artefact
- Domain
- Packaging & Assembly, Substrates
Overview
A package design kit does for a package technology what a process design kit does for a wafer process. It holds the assembly design rules, the substrate or interposer design rules, the stack-up and material data, electrical, thermal and mechanical models, bump and pad libraries, rule checking decks and reference designs, with the limits of each stated.
How it works
The kit is built once the process flow is frozen and the technology has been characterised on test vehicles. Its rules come from what the assembly line can build reliably, such as minimum bump pitch, die to die spacing, keep-out zones and substrate line and space. Its models are correlated with measurements on test vehicle hardware.
Customers design the package and the die's bump and pad layout to the kit, then run its checking decks before sign-off. As the technology matures, new kit versions tighten rules, add models correlated to more hardware and fix errors, each with release notes.
A kit is often released at more than one maturity: an early version for design studies and a released version once the technology is qualified, with the version a design used recorded with it.
Examples
- A kit for a fan-out technology with redistribution layer rules and a bump library.
- Interposer design rules and extraction models for a 2.5D technology.
- Assembly design rules for a fine-pitch flip chip package on a build-up substrate.
- A kit update that adds a thermal model correlated to new test vehicle data.
Why it matters
Package designers, chip designers working on bump and IO planning, and signal, power and thermal engineers use the kit. It sits in the package technology lifecycle after process integration and reliability qualification, and it is the point at which customer product designs can start on the technology.
It matters most to: Chip-Package-System Co-Design Engineer, Package Design Engineer, Package Layout & Substrate Design Engineer, Packaging Design Kit Engineer
Common confusions
- Not the same as PDK
- A PDK describes a wafer process and is used to design the die; a package design kit describes a package technology and is used to design the package and the die's connections to it.
- Not the same as Package substrate
- The substrate is a physical part of the package; the design kit holds the rules and data for designing that substrate and the rest of the package.
Sources
- Package Assembly Design Kits: What are They and How Can They Benefit the Packaging Community (IMAPS Device Packaging Conference 2021) (opens in a new tab), IMAPS (International Microelectronics Assembly and Packaging Society), 2026-11-10
- IHP Open Assembly Design Kit (ADK) documentation (opens in a new tab), IHP Leibniz Institute for High Performance Microelectronics, 2026-11-10
- AIM Photonics Introduces Assembly Design Kit to Streamline Photonic Packaging Design (opens in a new tab), Manufacturing USA, 2026-11-10
- Assembly Design Rules Slowly Emerge (opens in a new tab), Semiconductor Engineering, 2026-11-10
Related terms
Part of the Packaging & Assembly glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 2 pages of the Hub. In each group, the pages that mention it most come first.
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary