Out-of-order execution

Notes

Buys large IPC gains at significant power and area cost, which is why efficiency cores in heterogeneous clusters are often in-order or narrowly out-of-order.

Overview

Out-of-order execution is a processor design technique in which instructions run as soon as their inputs are ready, rather than strictly in the order the program lists them, while results are still made visible in program order. It lets a core keep busy with independent work while one instruction waits, for example on a cache miss. It is widely used in high-performance CPU cores, while simpler cores often execute in order and avoid its area and power cost.

How it works

Instructions are fetched and decoded in order, then their register names are renamed onto a larger pool of physical registers or reorder buffer entries. Renaming removes false dependencies, where two instructions merely reuse the same register name, so that only true data dependencies remain. Each renamed instruction waits in a scheduling structure, such as the reservation stations of Tomasulo's algorithm, and is sent to an execution unit once all its operands have arrived. Results are broadcast to any waiting instructions.

The reorder buffer keeps the machine correct. Every in-flight instruction has an entry, and the instruction at its head commits, updating architectural registers or memory, only when it has finished. If it has raised an exception, the pipeline is flushed so the exception appears at a precise point in the program. The same mechanism undoes instructions executed after a mispredicted branch, which is what allows speculative execution. Loads and stores add complexity, because a load may run ahead of an older store whose address is not yet known, so cores predict memory dependencies and check them later.

The benefits come with costs: deeper pipelines, a larger misprediction penalty, more power and area, and greater design and verification risk. Speculative execution also leaves traces in caches, which Spectre-class attacks exploit.

Examples

• BOOM, an open-source out-of-order RISC-V core whose reorder buffer commits up to its dispatch width of instructions per cycle.
• A loop on an Intel Core 2 Duo that, once tidied, ran at four instructions per cycle, as shown in an Imperial College lecture.
• The MIPS R10000, whose method of rolling back the rename map one reorder buffer row at a time is described as an option in the BOOM documentation.
• Spectre variant 1, which abuses speculative execution past a bounds check to leave a measurable cache footprint.

Why it matters

Out-of-order execution is a major reason modern application and server processors run ordinary code quickly, without relying on the compiler to schedule every instruction. CPU microarchitects size its buffers and widths, core design and verification engineers implement and prove it correct, performance architects model it, and security teams assess what its speculation may leak.

In the chip lifecycle, window sizes and issue widths are chosen during architecture with performance models, the logic is built and heavily verified at RTL because of its complexity and risk of design error, and the behaviour is tuned and characterised on first silicon.

It matters most to: CPU Core Design Engineer, CPU Microarchitect, Performance Architect, Processor IP Architect, Processor Verification Engineer

Common confusions

Not the same as superscalar execution

A superscalar core issues more than one instruction per cycle. It can do so in order or out of order; the two ideas are separate, though high-end cores combine them.

Not the same as out-of-order completion

The original Tomasulo design let results update state out of order, which made exceptions imprecise. Modern designs execute out of order but commit in order through a reorder buffer.

Not the same as compiler instruction scheduling

A compiler reorders instructions before the program runs, using what it can predict. Out-of-order hardware reorders at run time and can react to events such as cache misses that a compiler cannot foresee.

Sources

1. Dynamic scheduling, out-of-order execution, register renaming with speculative execution (Paul H J Kelly, Advanced Computer Architecture lecture notes, October 2023) (opens in a new tab), Imperial College London, 2026-10-22
2. The Reorder Buffer (ROB) and the Dispatch Stage (opens in a new tab), RISCV-BOOM documentation, 2026-10-22
3. Reading privileged memory with a side-channel (Jann Horn, 3 January 2018) (opens in a new tab), Google Project Zero, 2026-10-22
4. Meltdown and Spectre (opens in a new tab), Graz University of Technology (meltdownattack.com), 2026-10-22

Related terms

• Speculative execution
• Microarchitecture
• Superscalar
• IPC
• Branch prediction

Where it appears on the Hub

Used on 5 pages of the Hub. In each group, the pages that mention it most come first.