Jitter

Notes

The dual-Dirac model (DJ plus RJ) underpins nearly every high-speed compliance specification.

Overview

Jitter is the deviation of a signal's timing edges from where they should ideally be. In high-speed links and clocks it eats into the time available to capture each bit, so it is one of the main limits on data rates. Engineers split it into random jitter, which is unbounded, and deterministic jitter, which is bounded, so that they can predict error rates far lower than they can measure directly.

How it works

Random jitter comes from noise, such as thermal noise in transistors, and is unbounded: large deviations are rare but have no hard limit. Deterministic jitter comes from identifiable causes and is bounded. It includes data-dependent jitter, where a pattern of bits affects the edges that follow because of losses and reflections in the channel, periodic jitter from interference such as switching power supplies, and duty cycle distortion.

On an oscilloscope, jitter shows as a horizontal spread of the crossing points in an eye diagram, narrowing the eye. Because links must reach bit error ratios such as one error in 10¹² bits, too rare to measure quickly, engineers measure the distribution and extrapolate. The dual-Dirac model is a widely used method for estimating total jitter at a target bit error ratio from separate random and deterministic components.

Designers manage jitter on both sides of a link. Clock sources and PLLs are designed for low phase noise, transmitters use equalisation to reduce data-dependent effects, and receivers use clock and data recovery circuits that track slow jitter while tolerating fast jitter up to limits set by the interface standard.

Examples

• A jitter budget for a SerDes link dividing the allowed total among the transmitter, channel, reference clock and receiver.
• Measuring random and deterministic jitter on a transmitter output and comparing total jitter with the standard's limit.
• A receiver jitter tolerance test that adds sinusoidal jitter at increasing frequencies.
• Tracing periodic jitter on a clock to noise from a nearby switching regulator.

Why it matters

As data rates rise and voltage swings shrink, jitter becomes a large fraction of each bit's time, so jitter budgets drive SerDes, PLL and clock tree design. Interface PHY designers, clock and timing engineers, signal integrity engineers and validation and compliance engineers measure and budget it, and interface standards set jitter limits that products must pass.

In the chip lifecycle jitter budgets are set at architecture, verified by simulation during design, and measured on silicon during characterisation and compliance testing.

It matters most to: Clock and Timing Hardware Engineer, Compliance and Interoperability Test Engineer, SerDes Analog / PHY Design Engineer, SerDes and High-Speed I/O Validation Engineer

Common confusions

Not the same as skew

Skew is a fixed timing offset between two signals. Jitter is variation of one signal's edges over time.

Not the same as phase noise

Phase noise describes the same timing instability in the frequency domain, as noise power around a clock's frequency. Jitter describes it in the time domain. Jitter vs phase noise

Sources

1. Understanding and Characterizing Timing Jitter Primer (opens in a new tab), Tektronix, 2026-10-22
2. Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-Scale (white paper 5989-3206) (opens in a new tab), Keysight, 2026-10-22
3. Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes (Synopsys, 7 December 2022) (opens in a new tab), Semiconductor Engineering, 2026-10-22
4. Jitter (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• RJ
• DJ
• Jitter tolerance
• Jitter transfer
• Phase noise
• Random jitter

Where it appears on the Hub

Used on 38 pages of the Hub. In each group, the pages that mention it most come first.