PLL and Clock Generation Design Engineer

Project

Work done for a product or program.

• Design integer-N, fractional-N and all-digital PLL architectures including phase-frequency detectors, charge pumps, loop filters and dividers.
• Design LC and ring voltage-controlled oscillators, optimising phase noise, tuning range, KVCO linearity and supply pushing.
• Model loop dynamics in MATLAB or Simulink, setting bandwidth, damping and stability margin, then correlate against transistor-level PSS/Pnoise simulation.
• Analyse and suppress fractional spurs, reference spurs and delta-sigma quantisation noise through modulator order selection and dithering.
• Budget and verify jitter transfer, jitter generation and jitter tolerance against JESD204B/C, PCIe, or SONET/OIF clocking requirements.
• Characterise supply-induced jitter and design dedicated LDOs, deep n-well isolation and guard structures to meet integrated-jitter targets.
• Verify lock time, lock detect, band-select calibration and start-up across PVT and under aggressor activity from digital switching.
• Design clock distribution from the PLL output including dividers, duty-cycle correctors, clock gating and low-jitter buffers.
• Measure phase noise, integrated jitter and spur levels on signal source analysers during bring-up and correlate to simulation.
• Provide the clocking behavioural model and integration constraints to SoC teams, including supply noise and placement requirements.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain design guidelines, coding standards and reusable blocks.General
• Improve design flows and checks with the CAD and methodology teams.General
• Mentor newer engineers and share lessons learned across projects.General

Project

1. Produce and hand over the role's key deliverables
   • PLL/VCO schematics with loop parameter design document
   • Phase noise and integrated jitter budget with PSS/Pnoise signoff results
   • Locking, calibration and band-select verification matrix
   • Behavioural PLL model for full-chip AMS simulation
   • Silicon phase-noise correlation and characterisation report
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions