ESD protection (Electrostatic Discharge protection)

Notes

At RF inputs every extra femtofarad degrades noise figure and matching, so inductive or T-coil protection schemes are used.

Overview

ESD protection is the set of structures built into a chip, typically diodes and clamp circuits at the pins and between the supply rails, that give the current from an electrostatic discharge a safe path around the chip's delicate transistors. It is designed into input, output and supply pins so that the chip survives handling, assembly and testing, and it works alongside board-level protection once the chip is in a product. Designers must balance robustness against the area and performance the structures cost, which can be especially tight on high-speed, analogue and RF pins.

How it works

Two models describe the discharges a chip must survive. In the human body model (HBM), a charged person touches a pin; the test discharges a 100 pF capacitor through 1,500 ohms, giving a pulse that rises in a few nanoseconds. In the charged device model (CDM), the chip itself becomes charged, for example sliding down a feeder, and then discharges to metal in under a nanosecond with peak currents that can reach tens of amperes, enough to break gate oxides.

The protection must stay off during normal operation and switch on within that time, steering the current away from the circuits. At each pin this is typically done with diodes or similar devices that conduct to the supply or ground rails, and a power clamp between the rails absorbs the charge. Because the path must be low enough in resistance to keep voltages below what thin gate oxides can stand, foundries set resistance limits for every discharge path, and designers check them with reliability verification tools and, where margins are tight, with transient simulation.

Scaling makes the job harder: thinner gate oxides break down at lower voltages while contact and wiring resistance rise. Over-design costs area and can degrade performance and signal-to-noise ratio, so teams try to know their margins precisely. For chiplets, university research suggests that links between dies inside a package could use much simpler protection.

Examples

• Foundry rules limiting the resistance of every ESD discharge path, checked across a full chip with Siemens Calibre tools and context-aware SPICE simulation.
• Qualifying a new chip for HBM sensitivity to ANSI/ESDA/JEDEC JS-001 and CDM sensitivity to JS-002, which together replaced older machine model testing as the usual qualification set.
• System-level ESD tests to IEC 61000-4-2, which apply to finished equipment, so on-chip protection is backed up by protection on the board.

Why it matters

Related terms

• Guard ring
• Deep n-well
• LNA
• Insertion loss

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