D2W (Die to Wafer)

Notes

Requires sub-micrometre placement and extreme particle control, which is why collective die-to-wafer schemes are being developed.

Overview

D2W (die to wafer) bonding is a 3D assembly method in which individual dies, cut from one wafer and tested, are placed and bonded onto matching sites on another wafer that is still whole. It sits between die-to-die assembly and wafer-to-wafer bonding, combining wafer-level processing of the target with the freedom to choose which dies go where. Today it is most discussed for hybrid bonding, where copper pads and the surrounding dielectric are joined directly, but solder-based die-to-wafer stacking also exists.

How it works

The top wafer is thinned, prepared and singulated into dies; the target wafer stays intact. A die bonder then picks each die, aligns it to its site on the target wafer and places it. In hybrid bonding the surfaces must be extremely flat and clean, because the copper and dielectric bond directly: imec reports needing copper pad recess below 2.5 nm and used plasma dicing to singulate dies without particles. After placement, an anneal completes the copper bonds.

There are two main variants. In direct, or sequential, D2W each die is placed straight onto the target, one at a time. In collective D2W, dies are first arranged on a carrier wafer and then transferred to the target in a single wafer-level bond; EV Group demonstrated this with sub-two-micron placement accuracy in 2020.

The key advantages over wafer-to-wafer bonding are that only known good dies need to be stacked, which raises the yield of the finished stack, and that dies of different sizes and processes can be combined. The costs are throughput and accuracy: imec achieved a 2 micrometre copper pad pitch with die-to-wafer overlay errors below 350 nm in 2024, while wafer-to-wafer bonding already reaches pitches well below 1 micrometre. Semiconductor Engineering reported in 2022 that die-to-wafer hybrid bonding was much less mature than wafer-to-wafer.

Examples

• AMD's Ryzen 7 5800X3D, whose stacked cache was built with TSMC's SoIC hybrid bonding process.
• Imec's 2024 die-to-wafer hybrid bonding with a 2 micrometre copper pad pitch, presented at ECTC.
• EV Group's collective D2W process, in which dies are mounted on a carrier and bonded to the target wafer in one step.
• Stacking logic or memory dies on logic, which imec names as applications that fine-pitch D2W opens up.

Why it matters

D2W is how many 3D products stack chips that come from different processes or have different sizes, such as cache on logic or memory dies in a stack. Wafer bonding and 3D integration process engineers, die bonder equipment engineers, known good die test engineers and 3D-IC architects all depend on its accuracy, cleanliness and throughput, which together set cost and yield.

Related terms

• WoW
• CoW
• Hybrid bonding
• KGD

Where it appears on the Hub

Used on 4 pages of the Hub. In each group, the pages that mention it most come first.