Glossary comparison
SystemC vs SystemVerilog: what is the difference?
The difference
SystemVerilog is a hardware description and verification language used mainly at RTL. SystemC is a C++ library used mainly for higher-level models.
SystemC is a C++ library for system-level modelling and high-level synthesis. Despite the similar name it is a different language.
The two terms
SystemC
An IEEE 1666 C++ class library for modelling hardware and systems at transaction level, with an event-driven kernel, processes, ports and channels. It is the usual language for virtual platforms and architectural performance models.
SystemVerilog
The IEEE 1800 hardware description and verification language that extends Verilog with classes, constrained randomisation, functional coverage, assertions and interfaces.
Side by side
| Field | SystemC | SystemVerilog |
|---|---|---|
| Stands for | Not an abbreviation | Not an abbreviation |
| Type | Standard | Standard |
| Domain | Verification & Validation | Verification & Validation |
| Group | Testbench & methodology | Testbench & methodology |