Behavioural model

Overview

A behavioural model is a description of what a circuit block or system does, written at a higher level of abstraction than its transistors or gates, so that it simulates far faster than the real design. Teams use behavioural models to explore architectures, start software before hardware exists and check that analogue and digital parts work together. A model is only as useful as its agreement with the design it stands for, so it has to be checked against that design.

How it works

A behavioural model captures function and the timing or electrical behaviour that matters, and leaves out the internal structure. Several standard languages support this. SystemVerilog, defined in IEEE 1800, covers modelling at behavioural, register transfer and gate levels in one language. SystemC, a C++ class library defined in IEEE 1666, is used for system-level and transaction-level models of whole platforms. For analogue and mixed-signal blocks, Verilog-AMS from Accellera and VHDL-AMS (IEEE 1076.1) let engineers describe continuous-time behaviour, such as a filter response or a converter transfer curve, as equations rather than as transistor netlists.

The level of detail depends on the purpose. A virtual prototype models peripherals at transaction level, with registers that behave correctly but timing that is not exact, so that unmodified software can run at high speed on an ordinary computer. A mixed-signal verification model of a PLL or data converter keeps the behaviour that the surrounding logic depends on, such as lock time or output codes, so the top-level simulation can run in hours instead of days. Commercial simulators commonly link such models to RTL, for example through interfaces to SystemC, MATLAB and analogue simulation.

The main risk is drift between the model and the real circuit. Teams therefore compare model and transistor-level results over the operating conditions that matter, and update the model whenever the design changes.

Examples

• A virtual prototype of an SoC in which peripherals are SystemC transaction-level models, so firmware runs before the RTL is finished.
• A Verilog-AMS model of a phase-locked loop used in a top-level mixed-signal simulation in place of its transistor netlist.
• A SystemVerilog model of an external memory device inside an RTL testbench.
• A VHDL-AMS description of a sensor and its interface electronics used to check a complete measurement chain.

Why it matters

Behavioural models let architects compare options before committing to a design, let software teams start months earlier, and make full-chip mixed-signal verification practical. Behavioural modelling engineers, analogue and mixed-signal verification engineers, virtual prototyping teams and system architects all depend on them, and a wrong model can let a real bug through to silicon.

In the chip lifecycle, behavioural models appear at architecture for performance studies, during design and verification as stand-ins for blocks not yet built or too slow to simulate, and later as deliverables that customers use to integrate an IP block.

It matters most to: Analog Mixed-Signal Verification Engineer, Behavioral Modelling Engineer (Analog), Real Number Modelling Engineer, SystemC TLM Modeling Engineer, Virtual Prototyping Architect

Common confusions

Not the same as RTL

RTL describes registers and the logic between them cycle by cycle and is written to be synthesised into gates. A behavioural model may be far more abstract and is often not meant to be synthesised at all.

Not the same as a compact device model

Compact models, such as the BSIM family used in SPICE, describe how a single transistor behaves electrically. A behavioural model describes what a whole block or system does.

Related standards

• IEEE 1800 (SystemVerilog)
• IEEE 1666 (SystemC language reference manual)
• IEEE 1076.1 (VHDL analogue and mixed-signal extensions)
• Accellera Verilog-AMS 2023 (behavioural language for analogue and mixed-signal systems)

Sources

1. IEEE 1800-2023: IEEE Standard for SystemVerilog, Unified Hardware Design, Specification, and Verification Language (opens in a new tab), IEEE Standards Association, 2026-10-22
2. IEEE 1666-2023: IEEE Standard for Standard SystemC Language Reference Manual (opens in a new tab), IEEE Standards Association, 2026-10-22
3. IEEE 1076.1-2017: IEEE Standard VHDL Analog and Mixed-Signal Extensions (opens in a new tab), IEEE Standards Association, 2026-10-22
4. Verilog-AMS (Analog/Mixed-Signal) downloads (opens in a new tab), Accellera Systems Initiative, 2026-10-22
5. What is Virtual Prototyping? (opens in a new tab), Synopsys, 2026-10-22
6. VCS: Functional Verification Solution (opens in a new tab), Synopsys, 2026-10-22

Related terms

• Verilog-AMS
• TLM
• Virtual prototype

Where it appears on the Hub

Used on 7 pages of the Hub. In each group, the pages that mention it most come first.