Understanding transformer models well enough to make hardware decisions: attention and FFN compute and memory patterns, KV cache growth, arithmetic intensity by phase, quantization and sparsity behavior, and how prefill versus decode maps onto systolic arrays, HBM bandwidth and interconnect.
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Note from the research register: Learned by profiling real transformer workloads on accelerators in an AI hardware, compiler or performance role, on top of the original papers and current inference literature.
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