Analysing Vt distributions in NAND/NOR flash or logic devices: read-window margin between states, distribution broadening from program/erase cycling, retention and read disturb, and translating distribution shifts into read-level trim, ECC strength and endurance specs.
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Note from the research register: Memory device, characterization or product engineering role inside a NVM maker or controller team; learned with array characterization equipment over stress campaigns.
Register version 1.