Designing a phase-locked loop (PLL), a circuit that creates a stable clock at a chosen frequency from a reference, with low noise and jitter.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Analog and control courses, circuit simulation, and designing and testing PLLs in a chip.
Register version 1.