Using tools to prove that two versions of a design, such as RTL and gate netlist, behave identically, so no hidden errors are added.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Verification and synthesis courses, running tools like Conformal or Formality, and debugging mismatches.
Register version 1.