Estimating engineering effort for chip work — RTL and verification for a block, a PD closure cycle, a test program bring-up — with explicit assumptions, historical throughput data and a stated uncertainty range rather than a single date.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Learned by owning deliverables and then being held to your own estimates; improved by keeping a personal estimate-vs-actual log and by reference-class data from prior programs.
Register version 1.