Working familiarity with advanced package options and what each buys: flip-chip and wafer-level CSP, 2.5D interposer and CoWoS, fan-out RDL, HBM stacking, hybrid bonding and chiplet assembly, with their bandwidth, thermal, yield and cost implications.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Package, architecture or product role working with OSAT roadmaps, supplemented by ECTC/IEEE packaging literature.
Register version 1.