Analog Verification and Simulation Engineer

Project

Work done for a product or program.

• Convert block datasheets into executable verification plans with measurable checks per specification line.
• Develop analog coverage metrics and track specification coverage closure across the verification campaign.
• Write and maintain SystemVerilog or Verilog-AMS checkers and assertions for analog behaviour such as sequencing, thresholds and rail validity.
• Verify fault behaviour and safety mechanisms, including analog fault injection and fault-simulation campaigns for ISO 26262 diagnostic coverage.
• Validate behavioural and real-number models against transistor-level netlists and maintain the model equivalence regression.
• Own the analog verification signoff report and the residual-risk list presented at tapeout readiness reviews.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Build parameterised, reusable testbenches in Cadence ADE Assembler, Maestro or UVM-MS with self-checking measurement expressions.
• Set up and maintain corner, Monte Carlo, temperature and mode sweep regressions on compute farms, managing runtime and licence budgets.
• Automate results triage, waveform post-processing and report generation so failures are localised without manual waveform archaeology.
• Improve methodology and flows, including variation-aware techniques, machine-learning corner prediction and simulation runtime reduction.

Project

1. Produce and hand over the role's key deliverables
   • Analog verification plan traced to datasheet specifications
   • Reusable testbench library with self-checking measurements
   • Regression infrastructure and nightly/weekly results dashboards
   • Model-versus-transistor-level equivalence report
   • Analog fault simulation and diagnostic coverage report
   • Verification signoff report and residual risk list
2. Plan verificationGeneral
   • Extract the features to verify from the specification
   • Define coverage goals and the test strategy
   • Review the plan with design and architecture
3. Close verificationGeneral
   • Build testbenches and tests
   • Run and triage regressions
   • Report coverage and sign off

Function

1. Keep the methodology currentGeneral
   • Maintain reusable verification components
   • Update guidelines after each project
2. Improve the infrastructureGeneral
   • Reduce regression run time
   • Improve debug and coverage tools