Open-source repository register
The public code and data repositories chip design builds on, and for each part of each repository what the Hub itself may do with it. The mode is worked out from the licence the repository states, never typed in.
- Reuse
- The register's rule table accepts this licence for reuse, under the conditions listed.
- Cite
- The Hub links to and describes the repository and copies nothing from it.
- Watch
- The Hub records the repository and watches it, and does not describe it as something to build on.
The mode says what the Hub itself will do with each part. It is not legal advice and says nothing about whether you may use a repository in your own work or product. For that, read the licence and ask a lawyer. Find a licensing lawyer.
The Hub links to each repository and describes it. It does not host or mirror any code, data, model or release.
No place in this register can be bought. Inclusion, position, prominence and wording are not for sale, sponsorship, partnership or favour. The Hub records every request to buy one, with who asked and when, and refuses it.
EDA & Chip Design
All-in-one Docker/Podman image bundling the open-source IC design toolchain (Yosys, OpenROAD, Magic, KLayout, ngspice, Xschem, Verilator and more) for SKY130, GF180 and IHP130 analog and digital chip design. Curated by the Institute for Integrated Circuits (ICD), Johannes Kepler University (JKU) Linz. AMD64 and ARM64 natively supported.
Static analysis tool for detecting Clock Domain Crossing (CDC) issues in RTL designs — 2FF/3FF synchronizer detection, reconvergence and reset-domain hazards, SDC/YAML clock constraints, waiver workflow, and JSON/SARIF/HTML reports across 13 configurable rules (CDC001-CDC013).
Data Science & Simulation
Entries marked “Not yet in the register” show the licence as it was entered; until it is read at the source the Hub links and describes them and copies nothing.
What this register does not cover
Worked out from the register's own entries each time this page loads, not written by hand.
Categories with no open repository of substance
No category has a published absence yet.
Categories not yet researched
- EDA flows
- Open process design kits
- Processor cores and generators
- Simulation
- Test and verification tooling
- Machine learning for chip design
- Benchmark data
- Yield analysis
- Metrology and inspection
- Packaging warpage and stress
- Fab capacity data
- Repositories past their review dateThe read date on each record and the register's review interval.
- nothing to count yet
- Parts that derive ReuseThe licence each part states and the reviewed rule table.
- nothing to count yet
A repository missing here is one this register does not hold yet. Its absence says nothing about its quality.