TADA: Technology Aware DNN Accelerator Performance and Energy Estimator

Deep neural network (DNN) accelerators for edge inference must meet tight energy, latency, and area (EDP) constraints, and their optimal hardware architecture and dataflow configuration is typically identified through design space exploration (DSE). However, on-chip memory technology including cell type, bank organization, and process node, is rarely treated as a first-class citizen in DSE. For example, increasing memory capacity can reduce memory accesses through greater data reuse, but at the…

Source: arXiv cs.AR (Hardware Architecture), published 2026-11-03. The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern