Efficient Reconfigurable Architectures for Deep Learning

The growing computational demands of deep learning (DL) have driven AI-optimized reconfigurable devices, such as the AMD Versal AI Engines (AIEs), the Intel Stratix 10 NX Tensor Blocks (TBs), and the AMD Ryzen AI NPUs. Their heterogeneous resources and novel dataflow models make efficient exploitation nontrivial, and FPGAs lack native support for structured sparsity. This dissertation optimizes dense general matrix multiplication (GEMM), the dominant DL kernel, on these devices, proposes FPGA a…

Source: arXiv cs.AR (Hardware Architecture), published 2026-11-03. The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern