Saved captures from logic analysers built into the FPGA during bring-up and debug, with the trigger setup and notes on what they show.
Record or register Work product in the FPGA-based product development lifecycle
Internal logic signals cannot be probed on the board, so built-in capture is the main way to see what the logic does in hardware. Saving captures with their context lets others check conclusions, supports fixes and stops the same investigation being repeated.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.