The first packaged parts built from the first wafers of a new device, delivered for bring-up, validation and early test.
Physical item Work product in the FPGA chip development lifecycle and the Structured ASIC lifecycle
Bring-up and validation cannot start until packaged parts arrive. Knowing which lots and wafer positions the parts came from helps explain early results and plan characterisation.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.