How the test patterns are produced: test rule checks, ATPG for the agreed fault models with compression, BIST and boundary scan patterns, functional pattern capture, conversion to the tester format and simulation with tester timing. ATPG, DFT and test methodology engineers are its readers.

1. Purpose and scope

Patterns are most of a digital test program's content and much of its test time. This stage produces them from the final netlist and the test features the chip carries: structural patterns from ATPG for each agreed fault model, BIST and boundary scan patterns from their own descriptions, and functional patterns captured from verification. Each set is converted to the tester's format and simulated against the netlist with tester timing, so format and timing errors are found before silicon.

The stage runs alongside the chip's DFT insertion sign-off and physical design, and repeats when the netlist changes. It ends when every pattern set the program needs exists in tester format, has passed simulation, and has its coverage recorded against the goal.

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