1. Purpose and scope
Closure takes the frozen netlist and finishes it on the base. Logic and registers are formed in configurable cells near the fixed blocks and input and output cells they connect to, the connections are routed in the custom metal or via layers using the fixed routing where the base provides it, and the design's registers are connected to the fixed clock network. Nothing in the base can move, so the work is in the placement, the routing and, where needed, small changes limited to the custom layers.
Timing closure is the usual difficulty. Routing is limited to the custom layers and the fixed routing, and the clock network is fixed, so a design that looked close in the trial placement can still have critical paths that need placement guidance or an engineering change order. Every late change is kept to the custom layers where possible and is followed by a rerun of timing and equivalence. Test patterns are generated against the coverage goals frozen at the netlist freeze, and the final netlist is proven equivalent to the frozen one and through it to the agreed design.
There is much less to sign off than on a full custom chip, because the base layers were signed off once. What remains is this design: timing at every sign-off corner, the custom layer physical checks and the check of the full stack against the netlist, test coverage and equivalence. The stage opens at customer netlist freeze and closes at customer design sign-off, which sits on the Complete step of the maturity scale: the design is reviewed, tested and signed off for tape-out, with the customer's signature recorded.
12 more sections for registered members.