1. Purpose and scope
Two things are signed off in this stage and both are shared by every customer. The frozen base is verified like any chip: its fixed blocks, its clock and power networks, its test structures and its cells are checked against the base verification plan agreed at integration, and its physical checks are brought to the point where only tape-out findings remain. The design kit is verified by use: test designs, including the reference customer designs, are taken through the reference flow from netlist to custom layer data, because a kit that has only been reviewed and not used will fail on the first real customer.
The design kit is what customers and the vendor's own implementation team build on: the characterised configurable cell library with its timing and power models, the rules and physical verification decks for the custom layers, and a reference flow that takes a customer netlist through synthesis, test insertion, placement, routing, timing and physical checks to custom layer mask data. The kit is generated from the same source as the base database, so it always describes the base that is built.
The stage opens at base array design freeze and closes with two gates on the Complete step of the maturity scale: base array verification sign-off, which confirms the base is verified, and design kit released, which releases the kit with its maturity stated. The kit can be released while the base is still being taped out, so customer designs can be assessed and implemented in parallel. The base layer database itself is released in the next stage, Base Layer Tape-out & Wafer Banking.
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