1. Purpose and scope
The base array is designed once and shared by every customer device of each array size, so its design starts as a full custom chip with a regular structure. This stage lays out the configurable cell and the base tile, builds each array size from tiles, and brings in the production views of the fixed blocks: the embedded memories, the clock generators and the input and output ring. Each fixed block is connected to the clock spines and the power grid the architecture fixed, so that the base exists as one database rather than as a set of separate parts.
Two pieces of work run alongside the layout. The base verification environment is built from the frozen architecture, with its testbench, checkers and coverage model, and the base verification plan is agreed on the integrated base. And the reference customer designs chosen in Platform Definition are taken through a first, rough trial of the reference flow, from synthesis to placement and routing on the integrated base, so that timing and routing gaps show while the layout can still change. Neither is a sign-off: both are there to find problems early.
The stage opens after the base array architecture freeze and closes at base array integration complete. That gate sits on the Draft step of the lifecycle's maturity scale: the main content of the base exists and runs through a trial implementation, with its gaps listed. It also freezes the version and silicon status of each fixed block, because from here the cells and the routing around those blocks are finished against them in Base Array Design Completion.
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