1. Purpose and scope
After integration the base exists as one database, but it is not yet complete. The cells laid out in Base Array Design have no characterised models, the fixed layers still carry the gaps the trial flow found, and the test access every customer design will inherit is not yet in the base. This stage closes all three, until every planned feature is in and only reviewed fixes are accepted.
Library characterisation is the largest piece of work. Each configurable cell is simulated at the agreed process, voltage and temperature corners with the custom layer wiring that forms it, so that the timing, power and noise models describe the cell as a customer design will actually use it. The models are then checked against the layouts and against each other. The corners and model kinds chosen here decide how every customer design will be signed off, and they are released with the design kit at the end of the next stage.
The platform test architecture is also settled here: the scan access, memory self-test and boundary scan built into the base. A customer design cannot add test access to the fixed layers later, so it is built in and checked before the freeze. The stage opens at base array integration complete and closes at base array design freeze, which sits on the Feature complete step of the maturity scale: all planned content is in, and verification and fixes continue in Base Array Verification & Design Kit.
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